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C8051T610/1/2/3/4/5/6/7
SFR Definition 16.1. IE: Interrupt Enable
Bit
Name
Type
Reset
7
EA
R/W
0
6
ESPI0
R/W
0
5
ET2
R/W
0
4
ES0
R/W
0
3
ET1
R/W
0
2
EX1
R/W
0
1
ET0
R/W
0
0
EX0
R/W
0
SFR Address = 0xA8; Bit-Addressable
Bit Name
Function
88
7
6
5
4
3
2
1
0
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
Rev 1.1
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